1. Field of the Invention
This invention is in the field of manufacturing CMOS circuits using dried moat etchings to separate some portions of the active circuits, and conventional local oxidation of silicon (LOCOS) technology to separate other portions of the active circuits.
2. Description of the Prior Art
There are several possibilities of electrically insulating active regions, for example transistors, in integrated circuits such as in VLSI (very large scale integration) circuits from one another. The best known is that of local oxidation of silicon, usually referred to as LOCOS. In this type of technique, the insulation regions are thermally oxidized through the use of an oxidation mask composed, for example, of silicon nitride. Details of various types of LOCOS procedures will be found in the article entitled "Local Oxidation of Silicon; New Technological Aspects" by Appels et al appearing in Philips Research Reports, Vol. 26, No. 3, June 1971, pages 157-165. That publication is incorporated herein by reference.
It is extremely difficult to produce insulation ridges smaller than 1.5 microns with a standard LOCOS technique because of the appearance of the so-called birds beak structure. As explained in the aforementioned article, when no silicon is etched away before oxidation of the silicon surface under the layer of silicon nitride, an oxide beak is formed. This beak is due to a pronounced lateral under-oxidation and a pronounced outward diffusion of the field implantation ions. This results in a higher amplitude dependency of the threshold voltage of narrow transistors. In the article of Appels et al, previously cited, a method is disclosed in which a combination of a silicon nitride and a silicon dioxide layer serve first as a diffusion mask and then as an oxidation mask. The field oxides produced in this manner, however, still have many crystal defects which considerably disturb the electrical properties of the components manufactured therefrom. Further difficulties are presented in the lithographic dissolution process and in the silicon nitride etching.
In order to modify these limits of the LOCOS technology, a number of modified LOCOS type methods have been proposed.
In an article by I. Hui et al appearing in the IEDM Technical Digest 1982, pages 220-223, there is disclosed a method wherein the crystal defects are eliminated and the electrical properties are improved by what is referred to as SILO (sealed interface local oxidation). This article suggests the use of a sandwich type structure composed of plasma-generated silicon nitride, together with oxide and nitride layers produced by low pressure chemical vapor deposition (LPCVD).
A further method of this type is disclosed in an article by Chiu et al (IEDM Technical Digest, 1982, pages 224-227). This article describes what is known as SWAMI (sidewall masked isolation) technology, based on the use of a sloped silicon sidewall and thin nitride around the island sidewalls such that both intrinsic nitride stress and volume expansion induced stress are greatly reduced. An insulation layer measuring in the sub-micron range cannot be achieved by the methods of this reference.
One technique which can be used to produce insulation in such a narrow width is the trench technique set forth in detail in U.S. Pat. No. 4,139,442. This patent is also incorporated herein by reference. This patent describes the production of deeply recessed oxidized regions in silicon by forming a series of deep trenches by the use of a reactive ion etching method. Several different modifications are disclosed, depending upon the relative ratio between the width and the depth of the trench. From a technical standpoint, however, this process is extremely involved and requires substantial numbers of masking procedures.
In an article by Wang et al appearing in the IEEE Transactions on Electron Devices, Vol. ED-29, NO. 4, April 1982, pages 541-547, there is disclosed a trench etching technique for the isolation of VLSI circuits referred to as the "direct moat isolation" process. This article is also incorporated herein by reference. In this type of technology, the active device area is formed by patterning a thick field oxide uniformly on the silicon substrate. This type of direct moat isolation makes more efficient use of the silicon area by reducing encroachment considerably, thus allowing closer packing of active devices from the conventional LOCOS approach.